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HN29V128A1A (3.3 V/x8) HN29V128A0A (3.3 V/x16) HN29A128A1A (1.8 V/x8) HN29A128A0A (1.8 V/x16)
128M superAND Flash Memory (with internal sector management)
REJ03C0031-0300Z Rev. 3.00 Jun. 09, 2004
Description
The HN29V128A1A, HN29V128A0A, HN29A128A1A, and HN29A128A0A Series is a CMOS flash memory, which uses cost effective and high performance AND type multi-level memory cell technology. Current AND flash memory requires us to support complicated operations such as sector management for defect sector and error check correction. But this series doesn't need such operations. Beside it supports wear leveling function, which is sector replacement function in case of that certain sector, reaches certain erase/write times. And power-on-auto-read function is available. It enables to read the data of the lowest sector(2k byte) without command and address data input when power is on. Note: This product is authorized for using consumer application such as cellular phone, Therefore, please contact Renesas Technology's sales office before using other applications.
Rev.3.00, Jun.09.2004, page 1 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Features
* On-board single power supply (VCC): VCC = 2.7 V to 3.6 V (HN29V128A1A/HN29V128A0A) : VCC = 1.70 V to 1.95 V (HN29A128A1A/HN29A128A0A) * Operating temperature range: Ta = 0 to +70 C * Program/erase, rewrite endurance 105 times * Access time First access 80 s (typ) (3.3 V, x8/x16) 150 s (typ) (1.8 V, x8/x16) Serial read cycle 50 ns (min) (3.3 V, x8/x16) 100 ns (min) (1.8 V, x8/x16) maximum transfer rate (sequential read) 20.0 Mbyte/s (3.3 V, x8) 40.0 Mbyte/s (3.3 V, x16) 10.0 Mbyte/s (1.8 V, x8) 20.0 Mbyte/s (1.8 V, x16) * Program time 1.2 ms (typ) /sector (2048 byte) (3.3 V, x8/x16) 2.0 ms (typ) /sector (2048 byte) (1.8 V, x8/x16) * Erase time 2.2 ms (typ) /sector (2048 byte) (3.3 V, x8/x16) 3.5 ms (typ) /sector (2048 byte) (1.8 V, x8/x16) * Rewrite time 2.2 ms (typ) /sector (2048 byte) (3.3 V, x8/x16) 3.5 ms (typ) /sector (2048 byte) (1.8 V, x8/x16)
Rev.3.00, Jun.09.2004, page 2 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series * Low power dissipation (3.3 V and 1.8 V) Standby current ICCS1 = 1 mA (max) ICCS2 = 50 A (max) (CMOS level) ICCS3 = 10 A (max) (3.3 V), 15A (max) (1.8 V) (deep standby) Serial read operation current ICC1 = 30 mA (max) Program/erase/rewrite operation current ICC2/3/4 = 60 mA (max) (program/erase/rewrite) * Sector management Following functions are build-in flash memory component. Sector management: If certain sector had been damaged, it would be replaced by the spare sector automatically. Always 100% of sector number are available up to 105 erase/write cycles per device. Error check and correction: ECC code is generated at the time of programming, and data error is checked at the time of read operation. If data error occurs, the data will be corrected automatically. (ECC: 1-byte error correction, 2-byte error detection per 512byte page) Wear leveling: To avoid erase/program/rewrite operation converge on the particular physical sector, The number of erase/program/rewrite operation will be leveled automatically by changing internal logical sector address. * Package line up CSP: CSP 95-bump (TBP-95V)
Ordering Information
Type No. HN29V128A1ABP-5E HN29V128A0ABP-5E HN29A128A1ABP-8E HN29A128A0ABP-8E Operating voltage (VCC) Organization 3.3 V 3.3 V 1.8 V 1.8 V x8 x16 x8 x16 Package 10.0 x 11.50 mm2, 95-bump 0.8 mm ball pitch CSP (TBP-95V) Lead free
Rev.3.00, Jun.09.2004, page 3 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Pin Arrangement 95-bump CSP
95-bump CSP
1 A B C D E F G H J K L M
DU DU DU DU
2
DU DU DU DU DU
3
4
5
6
7
8
9
10
11
DU DU
12
DU DU
DU DU WE VSS
DU DU R/B DSE DU DU DU DU
DU DU DU DU DU DU DU DU
DU DU DU PRE I/O3 DU DU DU
DU
DU
VSS I/O8
DU I/O7
DU DU DU DU DU DU DU DU DU DU DU DU
I/O15 MRES I/O13 I/O6 I/O5 DU I/O1 DU DU DU I/O11 I/O9 DU VSS
I/O14 I/O16 DU VCC
DU DU DU DU DU DU
WP DU CLE ALE
I/O4 I/O12 I/O2 I/O10 DU RE DU CE
(TOP View)
Rev.3.00, Jun.09.2004, page 4 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Pin Description
Name I/O1 to I/O8 I/O9 to I/O16 CLE ALE CE RE WE WP R/B PRE MRES DSE VCC VSS DU Description Command, address, data input/output Data input/output (x8 device: DU) Command latch enable Address latch enable Chip enable Read enable Write enable Write protect Ready/busy Power on auto read enable Master reset output Deep standby enable Power supply Ground Don't use
Note: 1. All VSS pins should be connected respectively.
Rev.3.00, Jun.09.2004, page 5 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Pin Function
Chip enable :CE CE is for selecting a chip and making the device in the active state. During command waiting state, CE=H makes the device standby state. During command execution such as erase, program and rewrite, CE=H can't stop command operation itself. Read enable :RE RE is output enable pin and also controls read timing. Clocking RE increments the internal address and reads out each data. Write enable :WE Commands, address, and program data are latched into the device at the rising edge of WE. Command latch enable :CLE CLE specifies the command data. When CLE=H, data on I/O bus will be recognized as the command data. The command data is latched on the rising edge of WE with CLE=H. Address latch enable :ALE ALE specifies the address data. When ALE=H, data on I/O bus will be recognized as the address data. The address data is latched on the rising edge of WE with ALE=H. Write protect :WP WP=L disables erase, program and rewrite operation. Ready/busy :R/B R/B is the output signal. It shows the internal status of the device to be ready or busy. It is an open-drain signal and should be pulled up to VCC via suitable resistance. Power on auto read enable :PRE PRE is control pin with active high signal. PRE active Power on auto read mode and Auto read mode. If Power on auto read mode and Auto read mode are unnecessary, PRE pin should be connected to VSS or open. Master reset output :MRES MRES is the output signal and for providing a reset signal to CPU when Power on auto read mode and auto read mode are activated. MRES going from low to high indicates that the data is ready for reading. If Power on auto read mode and Auto read mode are not activated, MRES going from low to high indicates that the device initialization is completed after power is on. Deep standby enable :DSE DSE must be low when power is on. The device is initialized by DSE signal low to high after power is on. During command waiting state or standby state, DSE = L makes the device deep standby state. When DSE goes to high, the device returns from the deep standby state. During command execution, DSE = L stops command operation and makes the device deep standby state. Input/output pins :I/O1 to I/O16 The I/O pins are used as input/output data and also as command and address. I/O pins are tri-state pins and transit to the high impedance state when disabled by CE and RE. I/O9 to 16 are effective for x16 product, but they are applied for data only. Only I/O1 to 8 pins are used as command and address inputs for x16 product.
Rev.3.00, Jun.09.2004, page 6 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Block Diagram
VCC VSS Y-address counter I/O1 to x8 I/O8 I/O9 to x16 I/O16 R/B MRES CE CLE ALE WE RE WP PRE DSE
.....
Data input buffer Input data control
Data output buffer
Y-decoder Y-gating
Data register 2,048 Byte
Multiplexer
.....
Sector address buffer
...........................
Control signal buffer
Read/Program/Erase control
X-decoder
Memory matrix 8,192 x 2,048 x 8 8,192 x 1,024 x 16
Rev.3.00, Jun.09.2004, page 7 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Memory Map and Address
1FFF 1FFE 1FFD
Sector address
1FFF 1FFE 1FFD
Sector address
8,192
0002 0001 0000 512 bytes 2,048 bytes (x8 device) (1) x8 device Page size : (512) bytes Sector size : (2,048) bytes Total device capacity : 2,048 bytes x 8,192 sectors
0002 0001 0000 256 words 1,024 words (x16 device) (2) x16 device Page size : (256) words Sector size : (1,024) words Total device capacity : 1,024 words x 8,192 sectors
Address Input Case of HN29V128A1A/HN29A128A1A (x8 device)
Clock Cycle First cycle (CA1) Second cycle (CA2) Third cycle (SA1) Fourth cycle (SA2) I/O8 A7 L* A18 L* I/O7 A6 L* A17 L* I/O6 A5 L* A16 L* I/O5 A4 L* A15 A23 I/O4 A3 L* A14 A22 I/O3 A2 A10 A13 A21 I/O2 A1 A9 A12 A20 I/O1 A0 A8 A11 A19
Notes: 1. A0 to A8: Column address A11 to A23: Sector address 2. L* must be set to "Low".
A9 to A10: Page address
Case of HN29V128A0A/HN29A128A0A (x16 device)
Clock Cycle First cycle (CA1) Second cycle (CA2) Third cycle (SA1) Fourth cycle (SA2) I/O8 A7 L* A17 L* I/O7 A6 L* A16 L* I/O6 A5 L* A15 L* I/O5 A4 L* A14 A22 I/O4 A3 L* A13 A21 I/O3 A2 L* A12 A20 I/O2 A1 A9 A11 A19 I/O1 A0 A8 A10 A18
Notes: 1. A0 to A7: Column address A10 to A22: Sector address 2. I/O9 to I/O16: VIH or VIL 3. L* must be set to "Low".
A8 to A9: Page address
Rev.3.00, Jun.09.2004, page 8 of 49
8,192
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Mode Selection
The address input, command input and data input/output operations of the device are controlled by CLE, ALE, CE, WE, RE WP and DSE signals. The following table shows the operation logic table.
Mode Command input Address input Data input Data output Output deselect During rewriting/erasing Write protect Standby Deep standby CLE H L L L L x x x x ALE L H L L L x x x x CE L L L L L x x H x H H x x x x H x x x x WE RE H H H WP x x x x x H L x x DSE H H H H H H H H L I/O Input Input Input Output High-Z Input/ output Input/ output High-Z High-Z Power Active Active Active Active Active Active Active/ standby Standby*2 Deep standby*3
Notes: 1. H: VIH (DSE: VIHP), L: VIL (DSE: VILP), x: VIH or VIL 2. When setting CE = H during the read operation, even if it is in ready state, the device becomes the following data output waiting state and doesn't become standby mode. It becomes standby mode to set CE = H in ready state after read stop command execution. 3. The device can transfer only from command waiting state or standby state to deep standby state.
Command Definition
Mode Data input Read mode Sequential read mode Read stop Program Erase Rewrite Status read ID read Deep standby (release) Deep standby (setup) Note: First cycle 80H 00H 0FH F0H 10H 60H 1FH 70H 90H C1H C0H Second cycle D0H Acceptance Acceptance (in Read busy state only)*1 Acceptance in the busy state
1. Not acceptable during the busy state in the sequential read mode.
Rev.3.00, Jun.09.2004, page 9 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
State transition diagram
Power off VCC, DSE VCC, DSE
Deep standby (ICCS3) DSE DSE CE CE DSE DSE PRE PRE
Standby (ICCS1/2)
C0H C1H, Ready
Command deep standby (ICCS3)
PRE
70H Auto read Ready *SRD setup
RE
Status read
Ready,00H RE Data output RE
PRE Sector read-(Auto read) F0H PRE C O M M A N D W A I T I N G F0H Read RE Ready RE
Data output
Ready, 00H CA 00H Read setup Sequential CA read setup CA input SA CA input SA input SA SA input 70H SRD setup Sector End Ready, 00H F0H Sequential read PRE SA 60H Erase setup SA input Erase finish Data input setup CA CA input SA SA input Data input 10H 70H Program start D0H Erase start 70H 70H SRD setup RE RE Status read
0FH
Status read
80H
Program finish Rewrite finish Ready 70H RE *SRD setup RE 90H ID read setup Address input RE ID read Status read 1FH Rewrite start
70H
*SRD setup RE Status read
Note: SRD = Status read data
Rev.3.00, Jun.09.2004, page 10 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Absolute Maximum Ratings
If exceeded the following specification, the device may be damaged.
HN29V128A1A (3.3 V) HN29A128A1A (1.8 V) HN29V128A0A (3.3 V) HN29A128A0A (1.8 V) Parameter VCC voltage VSS voltage Input voltage Input/output voltage Symbol Value VCC VSS VIN VI/O -0.6 to +4.6 0 -0.6 to +4.6 -0.6 to VCC + 0.3 ( 4.6) 0 to +70 -55 to +125 Value -0.6 to +2.45 0 -0.6 to +2.45 -0.6 to VCC + 0.3 ( 2.45) 0 to +70 -55 to +125 Unit V V V V C C 3 1, 2 Notes 1
Operating temperature range Topr Storage temperature range Tstg
Notes: 1. Relative to VSS. 2. VIN, VOUT = -2.0 V for pulse width 20 ns 3. Device storage temperature range before programming.
Capacitance (Ta = +25C, f = 1 MHz)
Parameter Input capacitance Output capacitance Symbol CIN COUT Min Typ Max 10 10 Unit pF pF Test conditions VIN = 0 V VOUT = 0 V
Rev.3.00, Jun.09.2004, page 11 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
DC Characteristics
DC Characteristics (1) (Ta = 0 to +70C)
HN29V128A1A (3.3 V) HN29A128A1A (1.8 V) HN29V128A0A (3.3 V) HN29A128A0A (1.8 V) Parameter Symbol Min 2.7 VCC x 0.8 -0.3 VCC x 0.9 -0.3 Typ 3.3 Max 3.6 VCC + 0.3 VCC x 0.2 VCC + 0.3 VCC x 0.1 2 2 30 60 60 60 Min 1.70 VCC x 0.8 -0.3 VCC x 0.9 -0.3 Typ 1.8 Max 1.95 VCC + 0.3 VCC x 0.2 VCC + 0.3 VCC x 0.1 2 2 30 60 60 60 Unit V V V V V A A mA mA mA mA Test conditions VIN = 0 V to VCC VOUT = 0 V to VCC CE = VIL RE = VIH
Power supply voltage VCC High input voltage Low input voltage High input voltage (DSE, PRE pin) Low input voltage (DSE, PRE pin) VIH VIL VIHP VILP
Input leakage current ILI Output leakage current Operating current (Serial read) (Program) (Erase) (Rewrite) ILO ICC1 ICC2 ICC3 ICC4
Rev.3.00, Jun.09.2004, page 12 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series DC Characteristics (2) (Ta = 0 to +70C)
HN29V128A1A (3.3 V) HN29A128A1A (1.8 V) HN29V128A0A (3.3 V) HN29A128A0A (1.8 V) Parameter Standby current (Standby state) Symbol Min ICCS1 Typ Max 1 Min Typ Max 1 Test Unit conditions mA CE = VIH, WP = VIH or VIL, PRE = VIHP or VILP or open, DSE = VIHP A CE = VCC - 0.2 V, WP = VCC 0.2 V or VSS 0.2 V, PRE = VCC 0.2 V or VSS 0.2 V or open, DSE = VCC 0.2 V CE = VCC 0.2 V, PRE = VCC 0.2 V or VSS 0.2 V or open, DSE = VCC 0.2 V, WP = VCC 0.2 V or VSS 0.2 V CE = VCC 0.2 V, PRE = VCC 0.2 V or VSS 0.2 V or open, DSE = VSS 0.2 V, WP = VCC 0.2 V or VSS 0.2 V IOH = -100 A IOL = 100 A
ICCS2
50
50
Deep standby current (Deep standby command)
ICCS3
10
15
A
Deep standby current (DSE control)
ICCS3
10
15
A
High-level output voltage
VOH
VCC - 0.2

0.2
VCC - 0.2

0.2
V V
Low-level output voltage VOL
Rev.3.00, Jun.09.2004, page 13 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
AC Characteristics (Ta = 0 to +70C)
Test Conditions * VCC : 2.7 V to 3.6 V (HN29V128A1A(x8)/HN29V128A0A(x16)) : 1.70 V to 1.95 V (HN29A128A1A(x8)/HN29A128A0A(x16)) * Input pulse levels: 0 V, VCC * Input rise and fall time: 3 ns * Input and Output reference levels: 1/2 VCC / 1/2 VCC * Output load :
VCC
R1 = 3k Dout 50 pF R2 = 3k
Rev.3.00, Jun.09.2004, page 14 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series AC Characteristics (1)
HN29V128A1A (3.3 V) HN29A128A1A (1.8 V) HN29V128A0A (3.3 V) HN29A128A0A (1.8 V) Parameter CLE setup time CLE hold time CE setup time CE hold time CE high hold time Symbol Min tCLS tCLH tCS tCH tCEH 0 10 0 10 15 500 25 0 10 20 10 50 15 50 1 0 20 35 50 10 15 30 Typ Max 35 35 35 30 30 45 45 Min 0 20 0 20 25 1000 65 0 20 50 20 100 35 100 2 0 20 80 100 10 20 50 Typ Max 80 80 80 80 80 100 100 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 Note
CE high hold time in Sequential tCEHS read stop cycle Write pulse width ALE setup time ALE hold time Data setup time Data hold time Write cycle time WE high hold time RE high to WE low time RE high to WE low time in Sequential read cycle Ready to WP low time Ready to RE fall time Read pulse time Read cycle time RE access time (serial data access) RE access time (ID read) RE access time (Status read) Output data hold time RE high to output high-Z time CE high to output high-Z time RE high hold time CE access time CE access time (status read) WE high to CE low time tWP tALS tALH tDS tDH tWC tWH tRHW tRHWS tRW tRR tRP tRC tREA tREAID tRSTO tOH tRHZ tCHZ tREH tCEA tCSTO tWHC
Note: 1. tCEHS, tRHWS applies to Sequential read mode only.
Rev.3.00, Jun.09.2004, page 15 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series AC Characteristics (2)
HN29V128A1A (3.3 V) HN29V128A0A (3.3 V) Parameter Symbol Min 30 100 50 100 Typ 80 Max 250 200 200 WE high to RE low time tWHR ALE low to RE low time tAR1 (ID read) ALE low to RE low time tAR2 (read cycle) CE low to RE low time (ID read) tCR HN29A128A1A (1.8 V) HN29A128A0A (1.8 V) Min 100 100 100 100 Typ 150 Max 400 200 500 Unit ns ns ns ns s ns ns 1 Note
Start address access tR from memory cell array WE high to Busy output tWB time RE high to Busy output tSRB time in Sequential read cycle Power on to DSE High tDSE time DSE high to PRE high delay DSE high to busy time Power on busy time Ready to MRES high time Deep standby busy Auto read busy time PRE pulse width WP setup time WP hold time Read stop time CE high to WE low setup time tPD tDB tBSY tRMRES tDBSY tARBSY tPRE tWPS tWPH tRSTP tCHWS
0 50 100 100 0 5 5 5 5 5
5
50 5 30 50 300 1 250
0 100 100 100 0 5 5 5 5 10
5
100 5 50 100 500 1 400
ns ns ms ms ns s ms ns ns ns s ns ns ns ns s
WE high to CE low hold tWHCH time CE high to RE low setup tCHRS time RE high to CE low hold tRHCH time Ready to WE low time tRWS in Sequential read stop cycle
Note: 1. tSRB applies to Sequential read mode only.
Rev.3.00, Jun.09.2004, page 16 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Program/Erase/Rewrite Characteristics
(HN29V128A1A, HN29V128A0A: 2.7 V to 3.6 V, HN29A128A1A, HN29A128A0A: 1.70 V to 1.95 V, Ta = 0 to +70 C)
HN29V128A1A (3.3 V) HN29V128A0A (3.3 V) Parameter Rewrite time Erase time Program time Number of partial program cycles in the same sector Number of partial program cycles in the same page Note: Symbol Min tREWRITE tERS tPROG NPPS Typ 2.2 2.2 1.2 Max 100 100 30 4 HN29A128A1A (1.8 V) HN29A128A0A (1.8 V) Min Typ 3.5 3.5 2.0 Max 150 150 45 4 Unit ms ms ms cycles Note
NPPP
1
1
cycles
1. The data transfer time is not included.
Rev.3.00, Jun.09.2004, page 17 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Timing Waveforms
Power on and off
VCC min VCC 0V Don't care tDSE DSE 0V
CE, WE, RE, WP, CLE, ALE, PRE
Don't care
VIHP VILP tDB tBSY
VILP
Invalid R/B tRMRES Operation
MRES
Basic timing for command, address and data latch
CLE ALE RE
CE tCEH Setup time WE tDS
I/O1 to I/O8 I/O9 to I/O16 (x16)
tCEH Hold time
tDH DIN DIN
VIH or VIL
Rev.3.00, Jun.09.2004, page 18 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series Command input cycle
CLE CE
tCLS tCS
tCLH tCH
tWP WE
tALS ALE tDS I/O1 to I/O8 DIN
tALH
tDH
I/O9 to I/O16 (x16)
VIH or VIL
Rev.3.00, Jun.09.2004, page 19 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series Command input cycle after data output cycle
CLE tCLS tCS CE tWP WE tALS ALE tRHW, tRHWS RE tDS I/O1 to I/O8 I/O9 to I/O16 (x16) DOUT DIN tDH tALH tCLH tCH
DOUT
VIH or VIL
Rev.3.00, Jun.09.2004, page 20 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series Address input cycle
tCLS CLE tCS tWC tCH tCS tCH
tWP tALS ALE
tWH tALH
tALH
tDS tDH I/O1 to I/O8 I/O9 to I/O16 ( 16) VIH or VIL CA(1) CA(2) SA(1) SA(2)
Data input cycle
tCS CLE tWC tCH tCLH
tCS
tCH
tWP tALS ALE
tWH
tDS tDH I/O1 to I/O8 I/O9 to I/O16 ( 16) DIN0 tDS tDH DIN0 DIN1 DIN2 DIN M DIN1 DIN2 DIN M
VIH or VIL
Rev.3.00, Jun.09.2004, page 21 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series Serial read cycle
tCEA CE RE tRP tREH tOH I/O1 to I/O8 I/O9 to I/O16 (x16) R/B tREA DOUT tRR DOUT tREA DOUT DOUT DOUT tRHZ DOUT tCEA tCHZ
tRC VIH or VIL
Rev.3.00, Jun.09.2004, page 22 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series Invalid input cycle
CE
tCHWS
tWHCH
ALE CLE
WE
I/O1 to I/O8 I/O9 to I/O16 (x16)
DIN (Invalid)
VIH or VIL
Invalid output cycle
CE
tCHRS
tRHCH
ALE CLE
RE
I/O1 to I/O8 I/O9 to I/O16 (x16) VIH or VIL
Rev.3.00, Jun.09.2004, page 23 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series Status read This device automatically performs rewriting, programming, erasing, and verification after the operation. This device provides the status read function to indicate the device status and the execution result. The device status is output through the I/O pins by issuing command 70H then inputting the RE clock. The following timing shows the status as the output through the I/O pins. Status read cycle
tCLS CLE tCLS tCS CE WE RE tWHR tDS I/O1 to I/O8 I/O9 to I/O16 (x16) tDH tWP tWHC tRSTO tRHZ tCLH tCH tCSTO tCHZ
tOH Status output
70H
00H
VIH or VIL
Pin I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 to I/O16 Note:
Status Passed or failed Not used. Reserved for future use Not used. Reserved for future use Not used. Reserved for future use Not used. Reserved for future use Not used. Reserved for future use Ready or busy Write protection Not used
Output Passed: 0, failed: 1 0 0 0 0 0 Ready: 1, busy: 0 Protected: 0, not protected: 1 00H
1. The passed or failed status indicated through the I/O1 is only valid while the device is in the ready state.
Rev.3.00, Jun.09.2004, page 24 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series ID read This device holds the ID code which indicates the manufacturer and device information to the application system. The ID code can be read in the following timing. ID read cycle
tCLS CLE tCS CE tCLS tCLH tCH tCS tCH tCR
WE
tALH
tALS
tALH
tAR1
ALE
RE tDS I/O1 to I/O8 I/O9 to I/O16 tDH 00H tREAID
Manufacturer code
tREAID Device code
90H
07H
00H
00H
VIH or VIL
I/O8 Manufacturer code Device code I/O (x8) 3.3 V device I/O (x8) 1.8 V device 0 0 0
I/O7 0 1 1 1 1
I/O6 0 0 0 0 0
I/O5 0 1 1 1 1
I/O4 0 0 0 0 0
I/O3 1 0 0 0 1
I/O2 1 0 1 1 0
I/O1 1 1 0 1 0
Hexadecimal 07H 51H 52H 53H 54H
I/O (x16) 3.3 V device 0 I/O (x16) 1.8 V device 0 Note:
1. Output of I/O9 to I/O16 at manufacturer code and device code is "00H".
Rev.3.00, Jun.09.2004, page 25 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series Read mode The device enters into the read mode by command 00H. Read command operation is performed per every page. Start address in the page can be specified in a CA (Column address). The operating timing is shown below.
CLE CE WE ALE RE R/B N I/O 00H Read mode command CA1 CA2 Sector address SA1 SA2 N N+1 N+2 N+3 VIH or VIL Busy
Address input
Note : Read mode: When start address N is specified serial read is 512-N cycles in case of x8 or 256-N cycles in case of x16.
Rev.3.00, Jun.09.2004, page 26 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series Read cycle
CLE
CE WE tALH ALE tWB RE tALS tRR
N Sector address
tALH
tAR2 tRC tRHZ
I/O1 to I/O8 I/O9 to I/O16 (x16)
00H
CA1 CA2
SA1
SA2
DOUT N
DOUT N+1
DOUT N+2
DOUT M DOUT M
DOUT N
DOUT N+1
DOUT N+2
tR R/B
Note : M is end of page.
VIH or VIL
Rev.3.00, Jun.09.2004, page 27 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series Status read during the read operation The device status can be read out by inputting the status read command 70H in the read mode. Once the device has been set to the status read mode by 70H command, the device will not return to the read mode automatically. However, when the read command 00H is input after ready, the status read mode is reset and the device returns to the read mode. Status read during read mode
Ready
00H
Input address
70H
00H
R/B
RE
Output data
DOUT
DOUT
DOUT
DOUT
Status read mode
Normal read mode
Rev.3.00, Jun.09.2004, page 28 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series Read stop cycle Read stop command F0H enables to finish read mode. Read stop command F0H can be accepted in the busy state.
Read stop cycle Standby mode
Read cycle
CLE CE WE ALE RE
N Sector address
DOUT DOUT N N+1 DOUT DOUT N N+1 DOUT M DOUT M
Read Stop command
I/O1 to I/O8 I/O9 to I/O16 (x16) R/B
00H CA1 CA2 SA1 SA2
F0H
tWB
tRSTP
Note: M is end of page.
VIH or VIL
Rev.3.00, Jun.09.2004, page 29 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series Sequential read mode The device enters into the sequential read mode by command 0FH. This mode performs continuously reading through the pages and the sectors without additional command/address inputs. Start address in the page can be specified in a CA. The operating timing and block diagram are shown below.
CLE CE WE ALE RE R/B N I/O 0FH CA1 CA2 Sector address SA1 SA2 N N+1 M 0 1 M Busy
Sequential read command Note : M is end of sector.
Address input VIH or VIL
Column address N
Sector address
Start address
End of sector address (1FFFH)
Stop sequential read
Rev.3.00, Jun.09.2004, page 30 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series Sequential read cycle
CLE
CE WE tALH ALE tWB RE tALS
N Sector address
tALH
tAR2 tRC tRHZ
tRR
DOUT N DOUT N+1
I/O1 to I/O8 I/O9 to I/O16 (x16)
0FH
CA1 CA2
SA1
SA2
DOUT M DOUT M tSRB tR
DOUT N
DOUT N+1
tR
R/B Note : M is end of sector. VIH or VIL
Status read during the sequential read operation The device status can be read out by inputting the status read command 70H in the sequential read mode. Once the device has been set to the status read mode by 70H command, the device will not return to the sequential read mode automatically. However, when the read command 00H is input after ready state, the status read mode is reset and the device returns to the sequential read mode.
Ready 0FH Input address 70H 00H 70H Ready 00H
R/B RE Output data DOUT Status read mode DOUT DOUT DOUT DOUT Status read mode DOUT DOUT DOUT
Sequential read mode (Start sector data)
Sequential read mode (Next sector data)
Rev.3.00, Jun.09.2004, page 31 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series Sequential read stop cycle Read stop command F0H enables to finish sequential read mode. After inputting read stop command F0H, the device becomes busy state. And then, the sequential read mode ends and becomes command waiting state when the status returns to ready.
Stop after reading middle data of sector
Read stop cycle
tCLH
Sequential read cycle
CLE
tCH tCEHS
CE WE ALE RE
Sequential read command N Sector address Middle of sector data Read Stop command
tRHWS
I/O1 to I/O8 I/O9 to I/O16 (x16) R/B
0FH CA1 CA2 SA1 SA2
DOUT DOUT N N+1 DOUT DOUT N N+1
DOUT M-x DOUT M-x
F0H
tWB
tRSTP
Note: M is end of sector, x 1
VIH or VIL
Rev.3.00, Jun.09.2004, page 32 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series Stop after reading last data of sector
Read stop cycle
tCLH
Sequential read cycle
CLE
tCH
CE WE ALE RE
Sequential read command N Read Stop command
tCEHS tRHWS tRWS
Sector address
End of Sector
I/O1 to I/O8 I/O9 to I/O16 (x16) R/B
0FH CA1 CA2 SA1 SA2
DOUT DOUT N N+1 DOUT DOUT N N+1
DOUT M DOUT M tR tSRB
F0H
tRSTP
Note: M is end of sector
VIH or VIL
Rev.3.00, Jun.09.2004, page 33 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series Power on auto read / Auto read Power on auto read mode enables to read the data of the lowest sector(2k byte) without command and address data input when power is on. Auto read mode enables to read the data of the lowest sector (2k byte) without command and address data input in the normal operation. Power on auto read and Auto read are activated when power is on. Power on auto read is available and Auto read operates until power is off when these are activated. These are activated after PRE high signal right after DSE goes high. (DSE must be low until Power reaches VCCmin). MRES going low to high indicates that the data is ready for reading. The data of the lowest sector (2k byte) can be output by RE clock without command and address input. After power on read operation, PRE should be kept high. During the normal operation, keeping PRE low for tPRE makes the device transfer to the auto read mode and the data of the lowest sector (2k byte) can be output by RE clock without command and address input. If power on auto read and auto read operation is unnecessary, PRE pin should be connected to VSS or open. Power on auto read
VCC CLE CE WE ALE
VCC min
tDSE
DSE
VILP tPD
VIHP
PRE
VIHP
RE I/O1 to I/O8 I/O9 to I/O16 (x16) R/B
tRMRES
DOUT 0
tDB tBSY
DOUT 1 DOUT 1
DOUT 2 DOUT 2
DOUT M DOUT M
DOUT 0
MRES
Note : M 2047 (x8 device) M 1023 (x16 device)
Rev.3.00, Jun.09.2004, page 34 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series Auto read Case of tPRE < tARBSY
VCC DSE CE WE ALE CLE
VIHP
VIH VIL VIL
tPRE
PRE RE I/O1 to I/O8 I/O9 to I/O16 (x16) R/B MRES
Note : M 2047 (x8 device) M 1023 (x16 device) tWB
DOUT 0
tARBSY tRMRES
DOUT 1 DOUT 1
DOUT M DOUT M
DOUT 0
VIH or VIL
Rev.3.00, Jun.09.2004, page 35 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series Case of tPRE tARBSY
VCC DSE CE WE ALE CLE
VIHP
VIH VIL VIL
tPRE
PRE RE I/O1 to I/O8 I/O9 to I/O16 (x16) R/B MRES
Note : M 2047 (x8 device) M 1023 (x16 device) tWB
DOUT 0 DOUT 0
tRMRES
DOUT 1 DOUT 1
DOUT M DOUT M
tARBSY
VIH or VIL
Note:
1. When PRE is turned low during busy, after the operation performed now is completed, this device transfer to the auto read mode.
Rev.3.00, Jun.09.2004, page 36 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series Auto read (Deep standby mode which transferred by the command) Case of tPRE < tARBSY
VCC DSE CE WE ALE CLE
tPRE
VIHP
PRE RE I/O1 to I/O8 I/O9 to I/O16 (x16) R/B MRES
Note : M 2047 (x8 device) M 1023 (x16 device) tWB
DOUT 0
tARBSY tRMRES
DOUT 1 DOUT 1
DOUT M DOUT M
DOUT 0
VIH or VIL
Rev.3.00, Jun.09.2004, page 37 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series Case of tPRE tARBSY
VCC DSE CE WE ALE CLE
tPRE
VIHP
PRE RE I/O1 to I/O8 I/O9 to I/O16 (x16) R/B MRES
Note : M 2047 (x8 device) M 1023 (x16 device) tWB
DOUT 0 DOUT 0
tRMRES
DOUT 1 DOUT 1
DOUT M DOUT M
tARBSY
VIH or VIL
Rev.3.00, Jun.09.2004, page 38 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series Auto read stop cycle Read stop command F0H enables to finish power on auto read mode and auto read mode.
Read stop cycle Standby mode
Power on auto read mode or Auto read mode
CLE CE WE ALE RE
Read Stop command
VIL
I/O1 to I/O8 I/O9 to I/O16 (x16)
DOUT DOUT 0 1 DOUT DOUT 0 1
DOUT M DOUT M
F0H
tWB
tRSTP
R/B PRE
VIHP
Note : M 2047 (x8 device) M 1023 (x16 device)
VIH or VIL
Rev.3.00, Jun.09.2004, page 39 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series Program mode The program mode is organized by the data input and the program. Data input command 80H is for the input address and the program data. And program command 10H makes the device start the program (Please refer to the next page). The maximum data size is 2 kbyte (1 kword for x16 device). One sector is divided by 4 pages. The size of page is 512byte. Each page is programmable just one time as well as the normal 2 kbyte programming (Please refer to the figure below). The data at applied sector for program must be erased. The data of erased sector is [FF]. The programmed bits in the sector goes "1" to "0"when they are programmed.
0 to 2047 (x8 device) 0 to 1023 (x16 device)
0 0 Original data pattern in a sector Input data1
FF pattern
511 255
512 256
FF pattern
1023 1024 511 512
1535 1536 767 768
FF pattern
2047 1023
FF pattern
(x8) (x16)
Data1 Pattern after program
FF pattern
Data1
FF pattern
FF pattern
Input data2
Data2 Pattern after program
Data2
Data1
FF pattern
FF pattern
Note: Input only program data. It is not necessary to mask of the previous programmed data.
Rev.3.00, Jun.09.2004, page 40 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series Program cycle
CLE
CE
WE tWB ALE
RE
tPROG 80H
CA CA SA SA (1) (2) (1) (2)
Column address Sector address
I/O1 to I/O8 I/O9 to I/O16 (x16) R/B
DIN DIN N N+1
DIN DIN 10H M-1 M
70H
Output status data
DIN DIN N N+1
DIN DIN M-1 M
00H
Note : N M 2047 (x8 device) N M 1023 (x16 device)
VIH or VIL
Rev.3.00, Jun.09.2004, page 41 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series Erase mode The erase mode is entered by command 60H. After inputting sector address, command D0H erases the sector data. The erase size is always 2 kbyte and the erase operation must be done in the sector. Erase cycle
CLE
CE
WE tERS ALE tWB RE
I/O1 to I/O8 I/O9 to I/O15 R/B
60H
SA (1)
SA (2)
D0H
Status read command 70H
Status output
00H
VIH or VIL
Rev.3.00, Jun.09.2004, page 42 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series Rewrite mode The rewrite mode is organized by the data input and the rewrite. Data input command 80H is for the input address and the rewrite data to be changed. And rewrite command 1FH makes the device start the rewrite (Please refer to the next page). The maximum data size is 2 kbyte (1 kword in case of x16 device). By using rewrite, erase is automatically executed before programming, and the data can be rewritten for the sector. So the data before the programming operation can be either "1" or "0" (Please refer to the figure below).
N I/O 80H
Data input command
M Pass CA2 SA1 SA2 DIN DIN 1FH 70H
Status read command
CA1
I/O
Address
Automatic Data input 0 to 2047 (x8 device/sector) Rewriting 0 to 1023 (x16 device/sector) command
Fail
R/B 0 Original Data Pattern Input Data Pattern N
0 to 2047 (x8 device) 0 to 1023 (x16 device)
Data Pattern after rewrite
Rev.3.00, Jun.09.2004, page 43 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series Rewrite cycle
CLE
CE
WE tWB ALE
RE
tREWRITE 80H
CA CA SA SA (1) (2) (1) (2)
Column address Sector address
I/O1 to I/O8 I/O9 to I/O16 (x16) R/B
DIN DIN N N+1
DIN DIN 1FH M-1 M
70H
Output status data
DIN DIN N N+1
DIN DIN M-1 M
00H
Note : N M 2047 (x8 device) N M 1023 (x16 device)
VIH or VIL
Rev.3.00, Jun.09.2004, page 44 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Notes on usage
1. Prohibition of undefined command input The commands listed in the command definition can only be used in this device. It is prohibited to issue a command that is not defined in the list. If an undefined command is issued, the data held in the device may be lost. 2. Limitation of command input in the busy state In the busy state, following two commands are acceptable. Do not issue any other command except below two commands. * Status read 70H * Read stop F0H (during read operation) 3. Commands that can be issued after the serial input command (80H) After the serial input command (80H) is issued, the rewriting and programming command (1FH, 10H) can be issued; do not issue any other command except 1FH and 10H after 80H. 4. R/B(Ready/busy) pin handing R/B is an open-drain output pin, and it should be pulled up to VCC with a resistance(more than 2k). 5. Notes on turning power on and off The input signal levels may be unstable after power is on or off. In order to prevent unexpected operation, use DSE as shown below.
VCC min VCC 0V Don't care tDSE DSE 0V
CE, WE, RE, WP, CLE, ALE, PRE
Don't care
VIHP VILP tDB tBSY
VILP
Invalid R/B tRMRES Operation
MRES
Rev.3.00, Jun.09.2004, page 45 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series 6. Notes on WP signal When WP is at the low level, the rewriting operation is disabled. When using WP to control the operation, satisfy the timing shown below.
Operation enable WE D IN WP R/B tWPS Operation disable WE D IN WP tWPH R/B tWPS 1st com 2nd com Erase 60H D0H Program 80H 10H Rewrite 80H 1FH
1st com 2nd com 1st com 2nd com
tRW
7. Notes on RE signal If the RE clock is sent before the address is input, the internal read operation may start unintentionally. Be sure to send the RE clock after the address is input.
Rev.3.00, Jun.09.2004, page 46 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series 8. Deep standby mode During command waiting or standby state, when DSE pin goes to low, the device transfers to deep standby state. When DSE goes to high, the device returns from the deep standby state. During command execution, going DSE low stops command operation. If DSE goes to low during erase/program/rewrite operation, the command operation is forced to terminate and the applied sector data is not guaranteed.
Standby state DSE Deep standby state tDBSY Standby state
R/B
When CE becomes high after the C0H command input, the state of this device transfers to the deep standby state. When CE becomes high after the C1H command input, the state of this device transfers from the deep standby state to the standby state.
Deep standby setup command Standby state DIN CE, WE R/B C0H Deep standby state C1H Deep standby release command tDBSY Standby state
Rev.3.00, Jun.09.2004, page 47 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series 9. Notes on the power supply down Please do not turn off a power supply in busy status. It is recommended to take either of following (1) or (2) measures on system side for unexpected power down. (1) Please set DSE=L when detecting the power down. And erase any sector after the power supply is on. The other sectors data is protected though applied sector data is invalid by doing this.
VCC
2.4V (3.3V device) 1.6V (1.8V device) 1ms min
DSE
(2) Please store the operation record for back up. When the power down is recognized to have occurred during erase/program/rewrite operation, erase applied sector after the power on. The other sectors data is protected though applied sector data is invalid by doing this.
Rev.3.00, Jun.09.2004, page 48 of 49
HN29V128A1A/A0A, HN29A128A1A/A0A Series
Package Dimensions
HN29V128A1ABP, HN29V128A0ABP, HN29A128A1ABP, HN29A128A0ABP Series (TBP-95V)
Unit: mm
B
10.00
0.20 S B
0.80
0.60
0.80
12 11 10 9
A
8 7 6 5 4 3 2 1 MLK J HGFEDCBA
11.50
A
INDEX
0.20 S A
4x
0.15
0.20 S
1.35
95 x 0.40 0.05 0.08 M S A B
S
0.20 0.05
0.10 S
1.2 Max
Details of the part A
Note: DatumA, B are defined as center line of terminal matrix.
Package CODE JEDEC JEITA Mass (reference value)
TBP-95V - - 0.25 g
Rev.3.00, Jun.09.2004, page 49 of 49
Revision History HN29V128A1A/HN29V128A0A/HN29A128A1A/HN29A128A0A Series Data Sheet
Rev. Date Contents of Modification Page 0.00 0.01 Jun. 10, 2002 Jun. 10, 2002 18 Description Initial issue Correct of page numbers Change of Timing Waveforms Sequential read mode, Sequential read cycle, Stop sequential read cycle Change of Description Change of Features Change of Ordering Information Change of Pin Description Change of Pin Function Change of Address Input Change of Mode Selection Change of Command Definition Change of Absolute Maximum Ratings Change of DC Characteristics Change of AC Characteristics Change of Program/Erase/Rewrite Characteristics Timing Waveforms Change of Status read cycle Change of ID read cycle Change of Read mode Change of Read cycle Change of Sequential read mode Change of Sequential read cycle Change of Stop sequential read cycle Change description for Program mode Change description for Erase mode Change description for Rewrite mode Notes on usage Change of description Change of Notes on WP signal Change format issued by Renesas Technology Corp. Change of Description Features Access time: Change of Serial read cycle Change of Low power dissipation Deletion of TSOP package (TFP-48DA) Addition of CSP package (TBP-95V) Ordering Information Deletion of HN29V128A1AT-50, HN29V128A0AT-50, HN29A128A1AT-80, HN29A128A0AT-80 Addition of HN29V128A1ABP-5E, HN29V128A0ABP-5E, HN29A128A1ABP-8E, HN29A128A0ABP-8E
0.02
Sep. 20, 2002
1 2 3 4 6 8 9 9 11 12 13 17 18
45
0.03
Jun. 06, 2003
4 2
3
Rev.
Date
Contents of Modification Page Description Pin Arrangement Deletion of 48-pin TSOP Addition of 95-bump CSP Change of Pin Description Change of Pin Function Address Input: Addition of notes3 Mode Selection: Addition of notes2, 3 Command Definition: Addition of Read stop Addition of State transition diagram Change of DC Characteristics (1), (2) AC Characteristics Change of Test Condition Change of AC Characteristics (1), (2) Change of Program/Erase/Rewrite Characteristics Timing Waveforms Change of Basic timing for command, address and data latch Addition of command input cycle after data output cycle Addition of Invalid input cycle, Invalid output cycle Change of Status read cycle Change of ID read cycle Addition of Read stop cycle Change of Sequential read stop cycle Addition of Power on auto read Change of Auto read (Deep standby mode which transferred the command) Change of Auto read Change of Rewrite cycle Notes on usage 2. Limitation of command input in the busy state: Change of description Change of 3. Commands that can be issued after the serial input command (80H) 4. R/B (Ready/busy) pin handing: Change of description Change of 5. Notes on turning power on and off Change of 6. Notes on WP signal Change of 8. Deep standby mode Package Dimensions Deletion of TFP-48DA Addition of TBP-95V Memory Map and Address Address Input (x8 device): Deletion of Notes3 Mode Selection: Change of Notes1 AC Characteristics(1) Addition of tCEHS tRHWS min: 200/250 ns to 1/2 s AC Characteristics(2): Deletion of tARAS
0.03
Jun. 06, 2003
4
5 6 8 9 9 10 12 14
17 18
45
49
1.00
Jul. 16, 2003
8 9 14
16
Rev.
Date
Contents of Modification Page Description Timing Waveforms Change of Timing Waveforms Change description for Power on auto read/Auto read Notes on usage Change of 5. Notes on turning power on and off AC Characteristics (2): Addition of tSRB Timing Waveforms Change of Sequential read cycle Sequential read stop cycle Change of Stop in Busy state
2.00
Aug. 26, 2003
18
45 16 18
3.00
Jun. 09, 2004
Command Definition Addition of Note:1 16 AC Characteristics AC Characteristics (2) Addtion of tRWS 32, 33 Timing Waveforms Sequential read stop cycle Change of Sequential read stop cycle Change of Stop after reading last data of sector
9
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1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
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